--------------------Top_Level-------------------------------------------
-- Title      : Top_Level
-- Project    : HSC-mic1
-------------------------------------------------------------------------------
-- File	      : Top_Level.vhd
-- Author     : Morten Stigaard Laursen	 <morten@morten-x60s>
-- Company    : 
-- Created    : 2009-05-06
-- Last update: 2009-06-04
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: TopLevel
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date	       Version	Author	Description
-- 2009-05-06  1.0	morten	Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.std_logic_unsigned.all;

entity Top_Level is
  generic (
    N : integer := 32);			-- Defines the bus with of the B-bus
  port (
    CLK_IN   : in std_logic;		-- Clk signal
    Reset_IN : in std_logic;		-- Reset
	 Input_port : in std_logic_vector(N-1 downto 0); --input port
	 output_port : out std_logic_vector(N-1	 downto 0); --output port
	 debug	  : inout std_logic_vector(35 downto 0) -- chipscope debug port
	 );

end Top_Level;

architecture Top_Level of Top_Level is

  constant SIMULATING : boolean := FALSE
    -- pragma translate_off
      or TRUE
    -- pragma translate_on
  ; 
  
  component CPU_register
    generic (
      N		   : integer;
      Has_RE	   : integer;
      Has_OE	   : integer;
      Has_MemRead  : integer;
      Has_MemWrite : integer);
    port (
      CLK_IN	  : in	std_logic;
      RE_IN	  : in	std_logic			:= '0';
      OE_IN	  : in	std_logic			:= '0';
      BusData_IN  : in	std_logic_vector (N-1 downto 0);
      BusData_OUT : out std_logic_vector (N-1 downto 0);
      mem_RE	  : in	std_logic			:= '0';
      MemData_IN  : in	std_logic_vector (N-1 downto 0) := (others => '0');
      MemData_OUT : out std_logic_vector (N-1 downto 0);
		debug : out std_logic_vector(N-1 downto 0)
		);
  end component;

  component MPC
    port (
      CLK_IN	 : in  std_logic;
      MBR_IN	 : in  std_logic_vector (7 downto 0);
      Addr_IN	 : in  std_logic_vector (8 downto 0);
      JMPC_IN	 : in  std_logic;
      JAMZ_IN	 : in  std_logic;
      JAMN_IN	 : in  std_logic;
      N		 : in  std_logic;
      Z		 : in  std_logic;
      MIR_ADR_in : in  std_logic_vector(8 downto 0);
      MPC_OUT	 : out std_logic_vector(8 downto 0));
  end component;

  component MBR_register
    generic (
      N : integer);
    port (
      MemData_IN  : in	std_logic_vector (7 downto 0);
      Uint_OE_IN  : in	std_logic;
      Sint_OE_IN  : in	std_logic;
      mem_RE	  : in	std_logic;
      CLK_IN	  : in	std_logic;
      BusData_OUT : out std_logic_vector (N-1 downto 0);
      MBR_OUT	  : out std_logic_vector (7 downto 0));
  end component;

  component ALU
    generic (
      N : integer);
    port (
      F0_IN	    : in  std_logic;
      F1_IN	    : in  std_logic;
      ENA_IN	    : in  std_logic;
      ENB_IN	    : in  std_logic;
      INVA_IN	    : in  std_logic;
      INC_IN	    : in  std_logic;
      SLL8_IN	    : in  std_logic;
      SRA1_IN	    : in  std_logic;
      BusData_A_IN  : in  std_logic_vector (N-1 downto 0);
      BusData_B_IN  : in  std_logic_vector (N-1 downto 0);
      BusData_C_OUT : out std_logic_vector (N-1 downto 0);
      SIGN_OUT	    : out std_logic;
      ZERO_OUT	    : out std_logic;
      CARRY_OUT	    : out std_logic);
  end component;

  component RAMB16_S18
    -- pragma translate_off
    generic
      (
	write_mode : string := "READ_FIRST"
	);
    -- pragma translate_on

    port (
      DO   : out std_logic_vector(15 downto 0);	 -- Port A 8-bit Data Output
      DOP  : out std_logic_vector(1 downto 0);	 --Port parity
      ADDR : in	 std_logic_vector(9 downto 0);	 -- Port A 11-bit Address Input
      CLK  : in	 std_logic;		-- Port A Clock
      DI   : in	 std_logic_vector(15 downto 0);	 -- Port A 8-bit Data Input
      DIP  : in	 std_logic_vector(1 downto 0);	 --Port parity in
      EN   : in	 std_logic;		-- Port A RAM Enable Input
      SSR  : in	 std_logic;		-- Port A Synchronous Set/Reset Input
      WE   : in	 std_logic		-- Port B Write Enable Input
      );
  end component;

  component RAMB16_S9
    generic (
      write_mode : string := "READ_FIRST");
    port (
      DO   : out std_logic_vector(7 downto 0);
  --    DOP  : out std_logic_vector(0 downto 0);
      ADDR : in std_logic_vector(10 downto 0);
      clk  : in	 std_logic;
      DI   : in	 std_logic_vector(7 downto 0);
  --    DIP  : in	 std_logic_vector(0 downto 0);
      en   : in	 std_logic;
      ssr  : in	 std_logic;
      we   : in	 std_logic);
  end component;
 component bytecode_test IS
	port (
	clka: IN std_logic;
	addra: IN std_logic_VECTOR(10 downto 0);
	douta: OUT std_logic_VECTOR(7 downto 0));
	END component; 
  component RAMB16_S36
    generic (
      write_mode : string := "READ_FIRST");
    port (
      DO   : out std_logic_vector(31 downto 0);
      DOP  : out std_logic_vector(3 downto 0);
      ADDR : in std_logic_vector(8 downto 0);
      clk  : in	 std_logic;
      DI   : in	 std_logic_vector(31 downto 0);
      DIP  : in	 std_logic_vector(3 downto 0);
      en   : in	 std_logic;
      ssr  : in	 std_logic;
      we   : in	 std_logic);
  end component;
  
component micro_code_rom IS
	port (
	clka: IN std_logic;
	addra: IN std_logic_VECTOR(8 downto 0);
	douta: OUT std_logic_VECTOR(35 downto 0));
END component;
  
  component RegisterScan 
  port (
    CLK : in STD_LOGIC := 'X'; 
    CONTROL : inout STD_LOGIC_VECTOR ( 35 downto 0 ); 
    TRIG0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
  --  TRIG1 : in STD_LOGIC_VECTOR ( 11 downto 0 ); 
    DATA : in STD_LOGIC_VECTOR ( 255 downto 0 ) 
  );
	end component;
	
	component mem_dump
  port (
    CLK : in STD_LOGIC := 'X'; 
    CONTROL : inout STD_LOGIC_VECTOR ( 35 downto 0 ); 
    TRIG0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); 
    DATA : in STD_LOGIC_VECTOR ( 54 downto 0 ) 
  );
end component;

  -----------------------------------------------------------------------------
  -- Busses
  -----------------------------------------------------------------------------
  signal Abus		  : std_logic_vector(N-1 downto 0) := (others => '0');	-- Contains the
					-- A bus
  signal Bbus		  : std_logic_vector(N-1 downto 0) := (others => '0');	-- Contains the
					-- B bus
  signal Cbus		  : std_logic_vector(N-1 downto 0) := (others => '0');	-- Contains the
					-- C bus
  signal MicroProgramAddr : std_logic_vector(8 downto 0)   := (others => '0');	-- Contains the address for the microprogram

  signal MIR : std_logic_vector(35 downto 0) := (others => '0');  -- Microprogram Data

  signal MBR_data : std_logic_vector(7 downto 0) := (others => '0');  -- Holds the data comming from the MBR register to the MPC

  signal ALU_N : std_logic := '0';	-- N from the ALU
  signal ALU_Z : std_logic := '0';	-- Z from the ALU

  signal BselDemux	       : std_logic_vector(15 downto 0)	:= (others => '0');  -- Contains the demuxes Bbus OE signal			:= '1';	 -- Constant High
  signal Memmory_Adr	       : std_logic_vector(N-1 downto 0);
  signal Memmory_data_to_MDR   : std_logic_vector(N-1 downto 0) := (others => '0');
  signal Memmory_data_from_MDR : std_logic_vector(N-1 downto 0) := (others => '0');
  signal Ram_data	       : std_logic_vector(31 downto 0)	:= (others => '0');
  signal constant_pool_data    : std_logic_vector(31 downto 0)	:= (others => '0');
  signal input_buffer	       : std_logic_vector(31 downto 0)	:= (others => '0');
  signal Output_buffer	       : std_logic_vector(31 downto 0)	:= (others => '0');
  signal GND		       : std_logic			:= '0';
  signal VCC		       : std_logic			:= '1';
  signal ByteCodeData	       : std_logic_vector(7 downto 0)	:= (others => '0');
  signal ProgramCounterAddress : std_logic_vector(N-1 downto 0)	:= (others => '0');
-------------------------------------------------------------------------------
-- Aliases
-------------------------------------------------------------------------------
  ---------------- B bus selections ----------------	
  alias Bsel		       : std_logic_vector(3 downto 0) is MIR(3 downto 0);
  alias ReMDR		       : std_logic is BselDemux(0);
  alias RePC		       : std_logic is BselDemux(1);
  alias ReMBRs		       : std_logic is BselDemux(2);
  alias ReMBRu		       : std_logic is BselDemux(3);
  alias ReSP		       : std_logic is BselDemux(4);
  alias ReLV		       : std_logic is BselDemux(5);
  alias ReCPP		       : std_logic is BselDemux(6);
  alias ReTOS		       : std_logic is BselDemux(7);
  alias ReOPC		       : std_logic is BselDemux(8);
  alias write_mem	       : std_logic is MIR(6);
  alias read_mem	       : std_logic is mir(5);
  alias fetch_mem	       : std_logic is mir(4);
  alias Select_MAR	       : std_logic is MIR(7);
  alias Select_PC	       : std_logic is MIR(9);
  alias Select_MDR	       : std_logic is MIR(8);
  alias Select_SP	       : std_logic is MIR(10);
  alias Select_LV	       : std_logic is MIR(11);
  alias Select_CPP	       : std_logic is MIR(12);
  alias Select_TOS	       : std_logic is MIR(13);
  alias Select_OPC	       : std_logic is mir(14);
  alias Select_H	       : std_logic is MIR(15);
  alias INC		       : std_logic is MIR(16);
  alias INVA		       : std_logic is MIR(17);
  alias ENB		       : std_logic is MIR(18);
  alias ENA		       : std_logic is MIR(19);
  alias F1		       : std_logic is MIR(20);
  alias F0		       : std_logic is MIR(21);
  alias SRA1		       : std_logic is MIR(22);
  alias SLL8		       : std_logic is MIR(23);
  ------------------ Jump And Mask ---------------- 
  alias JAM		       : std_logic_vector(2 downto 0) is MIR(26 downto 24);
  alias JAMZ		       : std_logic is MIR(24);
  alias JAMN		       : std_logic is MIR(25);
  alias JMPC		       : std_logic is MIR(26);
  ------------------ Next Address ---------------- 
  alias NEXTMICROADDR	       : std_logic_vector(8 downto 0) is MIR(35 downto 27);
  
	------------------Hardware debugging signals---
  signal debugport : std_logic_vector(255 downto 0);
  signal mem_dump_pointer : std_logic_vector(10 downto 0) := (others => '0');
  signal mem_dump_data : std_logic_vector(54 downto 0);
  alias PC_debug : std_logic_vector(N-1 downto 0) is debugport(255 downto 224);
  alias SP_debug : std_logic_vector(N-1 downto 0) is debugport(223 downto 192);
  alias LV_debug : std_logic_vector(N-1 downto 0) is debugport(191 downto 160);
  alias CPP_debug : std_logic_vector(N-1 downto 0) is debugport(159 downto 128);
  alias TOS_debug : std_logic_vector(N-1 downto 0) is debugport(127 downto 96);
  alias OPC_debug : std_logic_vector(N-1 downto 0) is debugport(95 downto 64);
  alias H_debug : std_logic_vector(N-1 downto 0) is debugport(63 downto 32);

  
  
  
begin  -- Top_Level

  Vcc <= '1';
  GND <= '0';

  with Bsel select
    BselDemux <=
    "0000000000000001" when conv_std_logic_vector(0, 4),
    "0000000000000010" when conv_std_logic_vector(1, 4),
    "0000000000000100" when conv_std_logic_vector(2, 4),
    "0000000000001000" when conv_std_logic_vector(3, 4),
    "0000000000010000" when conv_std_logic_vector(4, 4),
    "0000000000100000" when conv_std_logic_vector(5, 4),
    "0000000001000000" when conv_std_logic_vector(6, 4),
    "0000000010000000" when conv_std_logic_vector(7, 4),
    "0000000100000000" when conv_std_logic_vector(8, 4),
    "0000001000000000" when conv_std_logic_vector(9, 4),
    "0000010000000000" when conv_std_logic_vector(10, 4),
    "0000100000000000" when conv_std_logic_vector(11, 4),
    "0001000000000000" when conv_std_logic_vector(12, 4),
    "0010000000000000" when conv_std_logic_vector(13, 4),
    "0100000000000000" when conv_std_logic_vector(14, 4),
    "1000000000000000" when others;

  ALU_1 : ALU
    generic map (
      N => N)
    port map (
      F0_IN	    => F0,
      F1_IN	    => F1,
      ENA_IN	    => ENA,
      ENB_IN	    => ENB,
      INVA_IN	    => INVA,
      INC_IN	    => INC,
      SLL8_IN	    => SLL8,
      SRA1_IN	    => SRA1,
      BusData_A_IN  => Abus,
      BusData_B_IN  => Bbus,
      BusData_C_OUT => Cbus,
      SIGN_OUT	    => ALU_N,
      ZERO_OUT	    => ALU_Z,
      CARRY_OUT	    => open);

  MPC_1 : MPC
    port map (
      CLK_IN	 => CLK_IN,
      MBR_IN	 => MBR_data,
      Addr_IN	 => NEXTMICROADDR,
      JMPC_IN	 => JMPC,
      JAMZ_IN	 => JAMZ,
      JAMN_IN	 => JAMN,
      N		 => ALU_N,
      Z		 => ALU_Z,
      MIR_ADR_in => NEXTMICROADDR,
      MPC_OUT	 => MicroProgramAddr);
		
--  microcode : RAMB16_S36
--    port map(
--      DO   => MIR(31 downto 0),
--      DOP  => MIR(35 downto 32),
--      ADDR => mem_dump_pointer(8 downto 0), --MicroProgramAddr,
--      clk  => clk_in,
--      DI   => (others => '0'),
--      DIP  => (others => '0'),
--      en   => VCC,
--      ssr  => GND,
--      we   => GND);
		
microcode : micro_code_rom
	port map (
	clka => clk_in,
	addra => MicroProgramAddr, --mem_dump_pointer(8 downto 0), 
	douta => MIR);
	
  MAR : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 0,
      Has_MemRead  => 0,
      Has_MemWrite => 1)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_MAR,
      OE_IN	  => open,
      BusData_IN  => Cbus,
      BusData_OUT => open,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => Memmory_Adr);

  MDR : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 1,
      Has_MemWrite => 1)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_MDR,
      OE_IN	  => ReMDR,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => read_mem,
      MemData_IN  => Memmory_data_to_MDR,
      MemData_OUT => Memmory_data_from_MDR);

  Stack : RAMB16_S36
    port map (
      DO   => Ram_data(31 downto 0),
      DOP  => open,
      ADDR => Memmory_Adr(8 downto 0),
      CLK  => CLK_IN,
      DI   => Memmory_data_from_MDR(31 downto 0),
      DIP  => (others => '0'),
      EN   => VCC,
      SSR  => GND,
      WE   => write_mem);
		


  PC : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 1)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_PC,
      OE_IN	  => RePC,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => ProgramCounterAddress,
		debug => PC_debug);

  MBR : MBR_register
    generic map (
      N => N)
    port map (
      MemData_IN  => ByteCodeData,
      Uint_OE_IN  => ReMBRu,
      Sint_OE_IN  => ReMBRs,
      mem_RE	  => fetch_mem,
      CLK_IN	  => CLK_IN,
      BusData_OUT => Bbus,
      MBR_OUT	  => MBR_data);

--  byte_code_rom: RAMB16_S9
--    generic map (
--      write_mode => "READ_FIRST")
--    port map (
--      DO   => ByteCodeData(7 downto 0),
--      ADDR => mem_dump_pointer(10 downto 0), --ProgramCounterAddress(10 downto 0),
--      clk  => CLK_IN,
--      DI   => (others => '0'),
--      en   => '1',
--      ssr  => '0',
--      we   => '0');
 
 byte_code_rom : bytecode_test
	port map (
	clka => clk_in,
	addra => ProgramCounterAddress(10 downto 0), --mem_dump_pointer(10 downto 0), 
	douta => ByteCodeData(7 downto 0));
	
  SP : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 0)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_SP,
      OE_IN	  => ReSP,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => open,
		debug => SP_debug);

  LV : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 0)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_LV,
      OE_IN	  => ReLV,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => open,
		debug => LV_debug);

  CPP : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 0)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_CPP,
      OE_IN	  => ReCPP,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => open,
		debug => CPP_debug);

  TOS : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 0)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_TOS,
      OE_IN	  => ReTOS,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => open,
		debug => tos_debug);

  OPC : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 0)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_OPC,
      OE_IN	  => ReOPC,
      BusData_IN  => Cbus,
      BusData_OUT => Bbus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => open,
		debug => opc_debug
		);

  H : CPU_register
    generic map (
      N		   => N,
      Has_RE	   => 1,
      Has_OE	   => 1,
      Has_MemRead  => 0,
      Has_MemWrite => 0)
    port map (
      CLK_IN	  => CLK_IN,
      RE_IN	  => Select_H,
      OE_IN	  => Vcc,
      BusData_IN  => Cbus,
      BusData_OUT => Abus,
      mem_RE	  => open,
      MemData_IN  => open,
      MemData_OUT => open,
		debug => h_debug);

-- purpose: Muxes the signal from the correct device onto the databus depending on the Adr
-- type	  : combinational
-- inputs : Memmory_Adr
-- outputs: Memmory_data_to_MDR
  memmory_address_select : process (Memmory_Adr)
  begin	 -- process memmory_address_select

  end process;
  
  IO_buffer : process (clk_in)
  begin	 -- process memmory_address_select
    if (clk_in'event and clk_in = '0') then
				mem_dump_pointer <= mem_dump_pointer +1;
		input_buffer <= input_port;
		if (conv_integer(Memmory_Adr) < 512) then
			Memmory_data_to_MDR <= Ram_data;
		 end if;
	--	 if (Memmory_Adr >= 512) and (Memmory_Adr < 512+16) then
	--		Memmory_data_to_MDR <= constant_pool_data;
	--	 end if;
		 if (Memmory_Adr = X"00010000") then
			Memmory_data_to_MDR <= X"0000CAFE";
		 end if;
		 if (Memmory_Adr = X"00010004") then
			Memmory_data_to_MDR <= X"00000064";
		 end if;
		 if (Memmory_Adr = X"00010008") then
			Memmory_data_to_MDR <= X"000002e9";
		 end if;
		 if (Memmory_Adr = X"0001000C") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010010") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010014") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010018") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"0001001C") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010020") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010024") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010028") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"0001002C") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010030") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010034") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"00010038") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"0001003C") then
			Memmory_data_to_MDR <= X"00000000";
		 end if;
		 if (Memmory_Adr = X"FFFFFFFD") then
			Memmory_data_to_MDR <= input_buffer;
			if write_mem = '1' then
		Output_buffer <= Memmory_data_from_MDR;
			end if;
		 end if;
    end if;
  end process;
output_port <= output_buffer;
--Onchip debugging
  --pragma simulation_off
  g_SYNTHESIS_ONLY: if ( not SIMULATING ) generate
    -- Put debugging code that does not show up in simulation
  RegisterScan_inst : RegisterScan 
  port map (
    CLK => clk_in, 
    CONTROL => debug, 
    TRIG0 => ProgramCounterAddress(11 downto 0),
--    TRIG1 => MicroProgramAddr, 
    DATA => debugport
  );
  debugport(31 downto 24) <= MBR_data;
  debugport(23 downto 15) <= MicroProgramAddr;
  debugport(14 downto 6) <= Memmory_Adr(8 downto 0);
  debugport (5 downto 0) <= (others => '0');
   
  
--  memmory_dumpie : mem_dump
--  port map(
--    CLK => not clk_in,
--    CONTROL => debug, 
--    TRIG0 => mem_dump_pointer,
--    DATA => mem_dump_data 
--		);
	
--	mem_dump_data <= ByteCodeData(7 downto 0) & MIR(35 downto 0) & mem_dump_pointer;
  end generate g_SYNTHESIS_ONLY;
  --pragma simulation_on
end Top_Level;
